1. Field of the Invention
The present invention relates to a low-pass filter circuit. More specifically, the present invention relates to a low-pass filter circuit for use in a system for controlling a tuning apparatus employing a phase locked loop.
2. Description of the Prior Art
FIG. 1 shows a block diagram of a system for controlling a tuning apparatus employing a phase locked loop. Referring to FIG. 1, the system comprises a receiving antenna 1, a high frequency amplifier 2 coupled to the antenna 1, and a local oscillator 3 coupled to the high frequency amplifier 2. The local oscillator 3 comprises a tuning circuit including a coil and a voltage controlled variable capacitance device 12. Such a voltage controlled variable capacitance device may comprise a voltage controlled variable capacitance diode which is commercially available as referred to as "Varicap cap". The voltage controlled variable capacitance device 12 is connected to receive an output of a low-pass filter circuit 4. The input of the low-pass filter circuit 4 is connected from a phase comparator 5. The phase comparator 5 is connected to receive one input from a reference frequency signal terminal 11 and the other input from a programmable frequency divider 7. The programmable frequency divider 7 is connected to receive a frequency signal to be divided from a prescaler 8 and a frequency division ratio controlling signal from a central processing unit 6. The prescaler 8 comprises a frequency divider for frequency dividing the output from the local oscillator 3. Thus, the local oscillator 3, the prescaler 8, the programmable frequency divider 7, the phase comparator 5 and the low-pass filter 4 constitute a phase locked loop, as is well known. The frequency converted output obtained from the local oscillator 3 is supplied to a television signal processing circuit 9 and the output from the television signal processing circuit is supplied to a picture tube 10, which may comprise a cathode ray tube.
An oscillation output from the local oscillator 3 is first frequency divided by the prescaler 8 and the frequency divided output thus obtained from the prescaler 8 is supplied to the programmable frequency divider 7. The programmable frequency divider 7 serves to frequency divide the output from the prescaler 8 as a function of the data supplied from the central processing unit 6. The phase comparator 5 compares the phases of the frequency divided output from the programmable frequency divider 7 and the reference frequency signal from the output frequency signal terminal 11, whereupon the outout signal is supplied to the low-pass filter circuit 4. The output from the low-pass filter circuit 4 is supplied, as a tuning voltage, to the voltage controlled variable capacitance device 12 included in the local oscillator 3. As a result, the oscillation frequency of the local oscillator 3 is controlled to be a value determined by the data obtained from the central processing unit 6.
FIG. 2 is a schematic diagram of one example of a conventional low-pass filter circuit 4 for use in the system shown in FIG. 1. The low-pass filter circuit 4 shown in FIG. 2 comprises a resistor 13 having one input connected to an input terminal IN for receiving an input voltage Ei and the other end connected to an input 15a of a phase inverting amplifier 15 operable to be switchable and having a high input impedance, and a capacitor 14 coupled between the other end of the resistor 13 and the ground. The resistor 13 and the capacitor 14 constitute a low-pass filter. The inverting amplifying circuit 15 has the input 15a thereof connected to the other end of the resistor 13 and to the non-grounded end of the capacitor 14, while the output 15b of the inverting amplifier is connected to the output terminal OUT. The phase inverting amplifier 15 is shunted by a feedback circuit 16 having a predetermined time constant. The feedback circuit is coupled between the input 15a and the output 15b of the amplifier and further has a load resistor 17 coupled to the output 15b of the amplifier 15. The input voltage supplied to the input terminal IN is denoted as Ei and the output voltage appearing at the output terminal OUT is denoted as Eo.
In operation, a response rate in which the output voltage Eo is switched from a lower voltage to a higher voltage as a function of the data supplied from the central processing unit 6 and thus a function of the input voltage Ei supplied from the input terminal IN, is substantially determined by the time constant set in the feedback circuit 16. Therefore, in case where the time constant of the feedback circuit 16 is decreased to increase the response rate, a ripple component included in the output voltage Eo appearing at the output terminal OUT is increased, which adversely affects a reception state where the output terminal OUT is to be brought to a constant potential, referenced hereinafter as a normal or first reception state. On the other hand, in case where the time constant of the feedback circuit 16 is increased to decrease the response rate, while the ripple of the output voltage is decreased and any problem on the occasion of normal reception is eliminated, a disadvantage is caused on the occasion of transition in reception where the output potential appearing at the output terminal OUT is changed.
In order to solve such dilemma, a conventional approach was to employ a value of the time constant of the feedback circuit which is determined as a compromise of the above described two requirements. As a result, there existed limits in simultaneously increasing a response rate and decreasing a ripple.